A device may use a local clock signal to facilitate receipt of an information stream, such as a data stream received via a high-speed serial interface. For example, FIG. 1 is a block diagram of a known system 100 in which a transmitter 110 provides a stream of information to a receiver 120. As illustrated in FIG. 1, an original signal 112 may be generated by the transmitter 110 in accordance with a transmit (Tx) clock signal. After the information travels through a channel 130 (e.g., a high-speed serial interface channel), a degraded signal 122 is received by the receiver 120. The receiver 120 may then re-create the original signal 124 in accordance with the received signal 122 and a local receive (Rx) clock signal.
To accurately re-create the original signal, the phases of the local Rx clock signal and the Tx clock signal as seen at the receiver 120 should be aligned as closely as possible. This is typically done by using the received information stream to “recover” information about the Tx clock signal. That is, “transitions” in the received information stream (i.e., from 0 to 1 or from 1 to 0) will reflect transitions in the Tx clock signal. By adjusting the local Rx clock signal in accordance with these transitions, the phase error between the local Rx clock signal and the Tx clock signal may be reduced.
When a received information stream does not contain a sufficient number of transitions (e.g., a data stream of “000000” is received), the receiver 120 may be unable to adjust the local Rx clock signal to track the Tx clock signal (as observed at the receiver 120). One way of avoiding this problem is to use an “8b10b” encoding scheme. In particular, an eight-bit pattern of original data is converted into a ten-bit pattern of data by the transmitter 110 (and the ten-bit pattern may provide at least a minimum transition density). The receiver 120 then converts each ten-bit pattern back into the original eight-bit pattern. The overhead associated with 8b10b encoding, however, reduces the efficiency of the system 100 (e.g., because ten bits must be transmitted to send eight bits of information).
As another approach, FIG. 2 is a block diagram of a known apparatus 200 that adjusts a local Rx clock signal. In particular, an amplifier 210 generates signals (e.g., D, I, and Q signals) based on a received information stream. Note that the amplifier 210 may comprise a number of amplifier units. For example, four amplifier units clocked in different phases may operate in parallel to provide data and information associated with where the data transition edges.
A vote generator, evaluation, and interpolator control unit 220 evaluates these signals and generates indications (“votes”) reflecting whether the local Rx clock signal should adjusted backward or forward. That is, a “backward” vote will be generated when received data appears to be transitioning before the local Rx clock signal. Similarly, a “forward” vote will be generated when received data appears to be transitioning after the local Rx clock signal. Based on these votes, digital logic in the unit 220 may provide appropriate control signals to an interpolator 230 to adjust the local Rx clock signal. For example, the interpolator 230 may receive four phases of a clock signal generated by a Phase-Locked Loop (PLL) device 240 in accordance with a core clock signal. The interpolator 230 may then generate and provide clock signals to the amplifier 210 based on information received from the unit 220.
Note the two data streams 250, 260 illustrated in FIG. 2. In the first data stream 250, data transitions frequently after a training period. As a result, the vote generator 220 will generate votes at a high frequency. In contrast, data transitions less frequently in the second data stream 260 (and the vote generator 220 will generate votes at a low frequency). Now consider the graph 300 of FIG. 3, which illustrates local Rx clock signal error as a function of transition density. When the transition density is very low (i.e., there are almost no data transitions), the error is very high because the vote generator 220 does not have sufficient information about the relationship between data transitions and the local Rx clock signal. As the transition density increases, the amount of error present in the local Rx clock signal can be reduced. Above a certain transition density, however, the error in the local Rx clock signal may actually increase. This may be, for example, because of a “loop delay” associated with local Rx clock signal adjustments. Referring again to FIG. 2, the “loop delay” represents an amount of time between receipt of a data transition and an associated adjustment to the local Rx clock signal. When the received data transitions too often, the indications from the vote generator 220 may be inaccurate depending on the loop delay and jitter response characteristics (e.g., the vote generator 220 might think that the local Rx clock signal is transitioning slightly too soon when it is really transitioning much too late). Thus, depending on the loop delay and the transition density associated with a received data stream, the performance of the system 100 might be degraded.